1. Field of the Invention
The present invention generally relates to testing and replacing defective devices through the use of fuses and more specifically to an on-chip fuse controller that provides a uniform interface for tester access across multiple chip designs.
2. Description of the Related Art
As technology advances, new process and design techniques extend our possibilities while simultaneously limiting the development and reuse of yesterday""s technology. This is the case for fuses. Historically, metal fuses were used for the storage of customization data and repair solutions of defects on silicon chips. Metal fuses required little area relative to devices and could be mechanically programmed with a laser. Today, the area required by metal fuses is significantly greater than the area consumed by the decreasing size of devices. Metal fuses cannot scale with device technology because of the size requirements needed to mechanically program fuses. Metal fuses also require a direct xe2x80x9cline-of-sightxe2x80x9d for laser access, which complicates the physical design methodology, since fuses may not be placed underneath overlying power busses.
There is an additional factor further complicating this dilemma: as devices decrease in size, it becomes possible to put more devices onto silicon, leading to smaller chips with larger memory arrays that require more fuses to repair defects. The area penalty of metal fuses is now more costly than ever. To further aggravate the problem, mechanical fuse programming requires that all customization and repair data be collected, and stored off-line after each test. Once all data has been collected it is compiled into a single repair solution and translated into XY coordinates corresponding to the fuse locations on the chip.
The customization, test and repair of complex chips in an automated manufacturing test environment with many unique ASIC designs are challenging problems. Initially, metal fuses were located in the individual macros requiring identification or repair. For repair, steps have been taken to isolate metal fuses into remote laser fuse bays. With the ability to store fuse data in a remote location, further steps were taken in both hardware design and test software to serially organize and compress the repair data for fuse storage. At system power-on reset and prior to post-fuse memory test, the fuse data is then decompressed into the original repair data form with the aid of an on-chip decompression system. This has helped reduce the penalty for using metal fuses, but has not eliminated the problem. In addition, the fuse system needs to accommodate varying device designs and types and numbers of memories as well as many diverse ATE Tool types.
The development of an electrically programmed fuse, or e-fuse, has opened the door to many possibilities. The e-fuse is manufactured as a polysilicon link and is significantly smaller than the metal fuse. It can also shrink in size with device technology, as the process continues to develop, because the e-fuse has fewer mechanical dependencies. Because the e-fuse is electrically programmed, it is now possible is to repair the chip multiple times; a first repair at 1 st pass wafer final test (WFT), a second repair at 2nd pass WFT, and a third repair during the final test of the packaged chip. A multiple repair capability provides leverage for testing and repairing memories across various temperatures.
The invention uses the e-fuse to enable on-chip self repair as part of a manufacturing test. The inventive on-chip self-repair includes new design requirements for all BIST engines responsible for finding memory defects and collecting repair data. It also provides a methodology for a tester 218 to communicate with a system controller 208 regardless of the uniqueness of each ASIC design. This methodology controls system initialization, collection of repair data, and a method of storing this data in fuses.
The invention provides an application specific integrated circuit (ASIC) chip which has memory elements, a plurality of fuses connected to the memory elements that can be programmed to replace defective memory elements with replacement memory elements, and a fuse controller connected to the fuses that can program the fuses. The fuse controller has a standardized test interface protocol for an external tester. The tester is presented with the same interface protocol irrespective of a design of the ASIC chip.
The fuse controller includes an instruction processor adapted to decode instructions from the tester. The fuse controller includes a repair data processing unit adapted to program said fuses. The invention has built-in-self-test (BIST) units connected to the memory elements and fuse controller. The BIST units are adapted to test the memory elements.
The fuse controller includes a repair data processing unit adapted to initiate the BIST units. The invention has repair registers connected to the BIST units, which are adapted to collect repair data relating to the defective memory elements. The repair data processing unit determines lengths of the repair registers. The repair data processing reads and decompresses fuse data prior to initiating the BIST units. The repair data processing collects and compresses repair data after the BIST units test the memory elements. The repair data processing interrogates the actual compressed data to count the number of logical xe2x80x9conesxe2x80x9d present (e.g., a count of the repairs needed), which represents the number of fuses needing to be programmed. A fuse program count value is relayed to the tester, so that fuse programming time may be minimized. The fuses comprise e-fuses. Each of the fuses includes a fuse skip multiplexor adapted to cause fuses that are not to be programmed to be passed over during fuse programming.
The invention also provides a method for programming fuses to replace defective memory elements with replacement memory elements on an application specific integrated circuit (ASIC) chip. The invention issues instructions from an external tester to a fuse controller on the ASIC chip. The fuse controller has a standardized test interface protocol. The tester is presented with the same interface protocol irrespective of a design of the ASIC chip. The invention decodes the instructions using the fuse controller. The invention then tests memory elements on the ASIC to identify the defective memory elements using the BIST units under control of the fuse controller. The invention also programs the fuses using the fuse controller.
The decoding is performed using an instruction processor within the fuse controller. The programming of the fuses is performed using a repair data processing unit within the fuse controller. The testing comprises initiating built-in-self-test (BIST) units using the repair data processing unit. The invention reads and decompresses fuse data prior to initiating the BIST units using the repair data processing unit. The invention collects repair data relating to the defective memory elements in repair registers and determines lengths of the repair registers using the repair data processing unit. The invention determines a time needed to program the fuses based on the number of logical xe2x80x9conesxe2x80x9d present in the actual compressed fuse data. After the testing of the memory elements, the invention collects and compresses repair data using the repair data processing unit. The invention passes over fuses that are not to be programmed during the programming of the fuses using a fuse skip multiplexor.